The present invention relates to video signal processor for processing video data.
Standards for interfaces for use in transmitting video signals as digital data are known. Typical standards are the digital visual interface (DVI) and the high-definition multimedia interface (HDMI).
In these standards, multiple transmission rates are defined, and thus many devices receiving video data need to operate based on clocks with frequencies associated with the respective transmission rates of the video data.
An example of a PLL circuit which outputs clocks with frequencies associated with input signals is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-261958. An example of a signal transmission device for transmitting signals using high-speed and low-speed serial buses is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2001-251385.
Devices receiving video data are not necessarily designed to process signals for all the transmission rates defined by the standards. For example, to avoid increase in cost, video signals with high transmission rates are left out of objects to be processed in some cases. However, a video signal with an unexpected-high transmission rate can be input without knowing that.
In a case where a video signal with a high transmission rate is input, a circuit tends to operate in accordance with a high-speed clock associated with the input signal. Accordingly, if a video signal higher than a speed predetermined in the design is input, the circuit malfunctions or excessive heat is generated. In particular, to release heat generated by the circuit, it is necessary to provide a heat sink or the like having sufficient ability. This causes another problem of increase in cost.